EDA News Monday April 21, 2003 From: EDAToolsCafe _____ CareersCafe.com _____ About This Issue From Margaret Mead to Caesar's Wife A chat with the DAC 2003 Chair Ian Getreu _____ April 14-18, 2003 By Peggy Aycinena Read business product alliance news and analysis of weekly happenings _____ DAC 2003 Chair Ian Getreu collects quotes and one of his favorites is from 20th century anthropologist Margaret Mead: "Never underestimate the power of a few committed people to change the world. Indeed, it is the only thing that ever has." Getreu has clearly taken that advice to heart over this past year in heading up the Executive Committee that will be running the 40th annual Design Automation Conference from June 2nd through 5th in Anaheim, CA. Getreu has thrown himself wholeheartedly into the effort, but he's quick to point out that everybody else must get the credit for a job well done. "Like any activity, you get good people and then you get out of their way. I've been very fortunate to have had lots of good people helping me all year long. The people on the DAC Executive Committee have been great. Also [DAC founders] MP Associates does a superb job. They know the ropes and that helps considerably. And Fleishman-Hillard [DAC PR] also has many years' experience working DAC, which also helps the Executive Committee." Getreu explains that the DAC Executive Committee has eight members, starting with two reps from each of the three principle show sponsors. There are two from ACM Sigda, two from the IEEE Circuits and Systems (CAS) Society, and two from EDAC. These six individuals constitute the SCC (Sponsor Coordinating Committee), which was formed to eliminate redundant DAC efforts within each of the three sponsoring organizations. The last two members of the DAC Executive Committee are the current DAC Chair and the previous DAC Chair. Officially, the "employer" of the committee is MP Associates, Inc. (founded by Pat and Marie Pistilli, now retired). Getreu says that MP Associates (now represented by Lee Woods and Kevin Lepine) also wears an "informal hat" whereby they serve in an advisory role to the Executive Committee. Getreu came to his involvement with DAC by way of his work as the IEEE CAS representative to the SCC. Eventually, he became Chair of the SCC, then was Publicity Chair for the DAC Executive Committee, and finally was named DAC Chair for 2003. He says, "Although most people usually come to be DAC Chair through a natural progression which includes work on the Technical Program Committee, I did not come up through the Technical Program. Circumstance was such that they just asked me to take this role. In either case, I've been on the DAC Executive Committee for many, many years." Getreu says that although attendance this year may not match the DAC 2000 attendance - which was the all time record - he's "dangerously optimistic" that there will be an excellent turn-out in Anaheim. "L.A. is a strong technical market, as is the entire West Coast. There are lots of electronics companies, particularly in the defense area, in Southern California. I'm hoping the economy will be doing better [by June], and that should help also." Getreu patiently answers the usual questions about the wisdom of holding DAC in New Orleans - an area notably under-populated by high-tech design companies. He says, "The decision to go to New Orleans [in 1999 and 2002] was made quite a few years ago. Last year, there was an unlucky confluence of events [reduced travel budgets and a faltering economy], but it was either hold the conference there or cancel it completely. We did not have a back-up [location] ready, so we went ahead with New Orleans. Now we're planning to stay on the West Coast - if you include Las Vegas - for some years." Getreu notes that it will be San Diego in 2004, Anaheim again in 2005, and then San Francisco in 2006. He notes that the San Francisco site was not available in June, so DAC 2006 will take place in July. [Mark your calendars accordingly.] Finally DAC 2007 will again be in Anaheim. He says there are few convention facilities in the U.S. large enough to accommodate DAC, so these dates need to be set years in advance. Getreu proudly points out that many new, creative policies and ideas were instituted last year at DAC 2002 in New Orleans. He says the current Executive Committee should be credited for innovation and for introducing fresh concepts that keep DAC evolving. According to Getreu, last year's changes included: - The DAC Pavilion - Hands-on tutorials - Monday tutorials - The Introduction to EDA Workshop for the non-technical professionals - Coffee carts on the floor He says the Committee's focus this year is on smoothing the details of last year's conference modifications. Additionally, the Executive Committee is spending a "significant amounts of time prepping for next year." Starting in 2004, there will be a major re-design on the show floor. Those companies who rent Demo Suites will have that space immediately adjacent to their Exhibitor Hall booth, and those combined facilities will be located around the periphery of the Exhibit Hall floor. Meanwhile, companies who only need an exhibit booth will be clustered in the center of the Exhibit Hall. Getreu says the DAC Pavilion this year will be showcasing a mock-up of the 2004 layout for everyone to see. He adds, "The format will be like a shopping mall where people who don't have suites will be positioned in the middle of the show floor." Meanwhile, there will be several new features introduced this year, as well. With the caveat that some of the details are not yet "nailed down," Getreu says additions will include: - More events in the DAC Pavilion - Changing the manner in which space selection occurs for the following year - Management Focus Day on June 3rd specifically for design and EDA companies - A designated area where design consultants can meet privately with potential clients - A Micro-brew event where vendors can provide their favorite beer - "Highlights of ISSCC" as reciprocity for ISSCC's "Highlights of DAC" Meanwhile, according to Getreu, the Student Design Contest will again be an important part of DAC this year. "We've worked over the years to take the original design contest run by the University of Michigan, [with leadership] from Richard Brown, and make it into the DAC Student Contest. The University of Michigan has always submitted a lot of papers, but now many other universities are submitting excellent papers as well. We have 51 papers this year, up from last year's 28. We'll be putting out a press release about the contest, plus we will be putting [a great deal of] money out for various scholarships and university programs." Getreu is notably enthused when he says, "We're going to be awarding $230,000 in scholarships in Anaheim this year." He says the awards will go to a range of students from high school to graduate-level participants. Not surprisingly, the DAC Executive Committee has decided to extend each afternoon's technical session by 30 minutes to allow time for even more submissions to be presented. "We made the decision to extend afternoons back in January when we realized we had a record number of paper submissions. We were faced with two choices. Either increase the number of papers accepted or increase the number of denials. Some people worried that if you make the sessions too long, it will be a problem, or will run into early evening activities. It was a difficult decision, but we believe this is the correct one." Does the Executive Committee struggle at times with the perception that considerations other than the technical merits of a paper or panel influence its selection for the DAC program? Getreu answers, "We have to do the Caesar's wife thing. We have to be both - fair and appear to be fair. We believe we are very fair, but that doesn't mean people don't complain. We are always willing to consider ideas that might improve the process and we encourage dialog about improvements." He adds, "I've been involved with DAC for many, many years. Maybe I'm unaware, but I don't see many complaints. I don't think people say, 'You're not fair. You didn't do the right thing.' I have never gotten that impression. To a certain extent we are influencing the direction of the technology and people on the Technology Committee tend to accept papers because they're good. I'm not going to claim every decision is correct, but the more people get involved, the more chances we'll have of making a good decision." Getreu has a specific vision of the type of papers that are appropriate for DAC: "ISSCC is about cutting edge papers in design. [On the other hand], DAC is not just EDA tools. I think the papers at DAC are about cutting edge [technology] in EDA and about design methods. I've made the analogy that design methodology and EDA tools are intertwined like DNA. The stronger the coupling, the stronger the resulting [organism]." With regards to his own technical interests at DAC, Getreu chuckles and says, "My own personal interest is in the analog and mixed-signal area. But again, I have to be like Caesar's wife. I must be interested - and maintain the appearance of being interested - in all of the technical topics covered at DAC. Of course, most of the time I'll probably be moving around the show floor or checking how things are going with the technical program." He adds with another chuckle, "I'll be working to convince myself that I'm important enough to do that." Is Getreu looking forward to anything in particular at DAC 2003? He answers, "I know this is trite and banal, but I'm just looking forward to a very, very successful DAC. There should be a lot of excitement, attendance should be up, and everybody should be very happy. Our committees are constantly striving to ensure that DAC is more than a trade show. It's a technical program as well, and there needs to be a balance. I'm particularly proud of the Executive Committee for last year and this year because of their ability to consider and implement changes." What does Getreu's own wife think of DAC? Getreu is unequivocal: "You ask if my family is supportive. I can't emphasize that enough. Without the strong support of my wife, I wouldn't have been able to do this job. She has been a tremendous help and support. And, although we are empty nesters, our kids have been very supportive as well." Finally, with some prodding, Getreu was willing to participate in the following exchange: "Ian Getreu! You've just finishing chairing DAC 2003! What are you going to do now?" Holding two thumbs up, Getreu flashes a smile for the camera and says, "I'm going to Disneyland!" Additional DAC info from Fleishman-Hillard DAC 2002 New Orleans attendance numbers: ˙˙Total attendees - 9452 ˙˙Exhibitors, visitors & guests - 4271 DAC 2003 Booth selection dates - Tuesday and Wednesday, June 3-4 DAC 2003 Management Focus Day to include: - Sir Robin Saxby's keynote address - Morning sessions focused on EDA issues for design managers of system house and semiconductor companies - The EDA Business Forum Lunch hosted by EDAC's Pam Parrish, with D.A. Davidson & Co.'s Bill Frerichs moderating the panel - Afternoon DAC Pavilion Panel, including "ARM Twisting: Ask Sir Robin" - EDA Business Forecast Highlights from 3 PM to 4 PM Interesting Geographical Note Ian Getreu is originally from Melbourne, Australia. Last year's chair, Bryan Ackland, is from Adelaide. Australia. A past chair from several years ago, Richard Newton, is from Melbourne, as well. DAC 2003 Chair Biographical Note Ian Getreu studied IC Design at UC Berkeley, where he did his Ph.D. from 1967 to 1972. Ian says, "It was a great time to be at Berkeley - Free Speech Movement, the birth of the hippie movement, Vietnam protests, the start of Silicon Valley, etc. This was also the time the simulation programs such as SPICE were developed at Berkeley. I was privileged to be in the middle of all that, although I didn't do any development myself. Just used them." Getreu believes his first DAC was at the Grand Old Oprey in Nashville, TN. (Editor's Note: Thanks to the ever-gracious Sonia Harrison, Senior Vice President at Fleishman-Hillard, for this information. Reports indicate this will be Sonia's 14th DAC.) News of note - Synopsys acquires Qualis, Inc. verification IP & Janick Bergeron Synopsys, Inc. announced it has acquired the verification IP assets of Qualis, Inc. and its affiliated companies, which perform verification methodology consulting and training. Synopsys plans to integrate Qualis' Domain Verification Component (DVC) technology into its DesignWare Verification IP. In addition - and possibly even more importantly - a number of key Qualis personnel will join the Synopsys team, including Janick Bergeron, Qualis, Inc.'s CTO and a recognized industry expert in the field of verification methodology. The purchase price for Qualis' assets was not disclosed. As a result of the transaction, the Qualis companies will discontinue sale and support of all existing Qualis products and will change their company names. Joachim Kunkel, Vice President of Marketing, Intellectual Property and Design Services for Synopsys, said: "Synopsys is committed to building the next-generation unified verification platform. As the complexity of on- and off-chip communications protocols continues to increase, verification IP has become an essential part of the testbench. By adding Qualis' verification technology and engineering talent, Synopsys is accelerating its ability to deliver advanced verification IP to its customers." Industry News - Tools & IP Altium Ltd. announced full support for Xilinx, Inc.'s Spartan-3 platform FPGAs. Nick Martin, Joint CEO and Founder of Altium, said: "At Altium, we see FPGAs as the platform of the future for electronics system design. With unprecedented density range and the lowest price points, Xilinx's new Spartan-3 platform FPGAs provide an ideal production platform for microprocessor-based systems on FPGAs. By supporting the Spartan-3 platform in upcoming versions of our nVisage products, we are providing the mainstream market of engineers easy access to these high-capacity FPGAs for development and production." Apache Design Solutions announced RedHawk-SDL (Static, Dynamic and L inductance), a full-chip cell-based power-ground design and verification tool with integrated transistor-level characterization. The tool analyzes the effects of on-chip and off-chip (package) inductance, simultaneous switching (core, memory and I/O), decoupling capacitance (intrinsic and intentional), and dynamic voltage drop impact on clock skew and timing. The product has a single-kernel architecture and is intended to help SoC designers analyze dynamic voltage waveforms at every instance on the full-chip power grid early in the design process, protect these areas with decoupling capacitance, and then verify full-chip power integrity. The company says RedHawk-SDL's full-chip runtime, from design input to final results display, is roughly two hours for 4 million gates (single CPU), including power calculation, power-grid RLC extraction, static IR/EM, transient voltage drop simulation, and decoupling capacitance analysis. Full-chip dynamic run of a 20-million gate SoC can be completed overnight. RedHawk-SDL is currently being used by early adopters in the U.S. and Japan on 90-nanometer and 130-nanometer production SoC projects. ARC International announced that LSI Logic Corp. has licensed its USB High-Speed On-the-Go (OTC) and device technology. LSI Logic says it will integrate the ARC technology into its CoreWare library of IP. ARM and Aptix Corp. announced that Aptix has joined the ARM EDA Partnership Program. The ARM EDA Partnership Program allows developers to choose from a variety of design tools from EDA vendors, with the knowledge that the tools are compatible with the ARM IP supplied with the tools. Aptix says it provides a combination of ARM Integrator Core Modules and the Aptix FPGA-based pre-silicon prototyping tool so that developers can complete software and hardware development before moving to silicon. Atrenta Inc. announced SpyGlass Constraints, a design tool that checks design constraint files, including SDC constraints, early in the design cycle. The company says that at the block level, SpyGlass Constraints finds problems related to timing. The product checks the consistency and completeness of the constraints in clock characteristics (waveform, latency, and transition times), that all clocks are constrained, that generated clocks are consistent with specified source clocks, that input and output constraints are consistent with destination or sourcing clocks, that drive (load) specifications are set for all inputs or outputs, and that timings exceptions are specified on stable points in the design. SpyGlass Constraints also includes a new visualization tool to create timing diagrams representing the constraints, intended to help the user check assumptions associated with timing requirements. Axis Systems, Inc. announced that Micronas has acquired additional Xtreme verification systems. The companies report that these additional systems will be distributed to three separate locations, replacing older competing technology, and will be used to verify SoC designs. Barcelona Design Inc. announced that it has expanded its synthesizable analog IP offerings. The company has completed comprehensive qualification, including silicon testing, of PLLs generated by its Miro Class 0.13-micron PLL engine, and targeted the IP at TSMC's 0.13-micron process. In a related announcement, the company said it has also extended the Miro PLL class to support the TSMC NexSys 90-nanometer process technology. Barcelona expects to release the production 90-nanometer Miro PLL engine in mid-2003. Icinergy Software announced the expansion of its pre-synthesis physical analysis, estimation, and optimization technology into a new three-product toolset - SoC Preview, SoC Plan, and SoC Prototype. The company says the new product configurations of its SOCarchitect technology address design flow needs for early-stage physical design of SoC products and complex ASICs, and also address communication needs for IC vendors, IP vendors, and design service houses for interaction with prospective customers. SoC Preview is a desktop physical design exploration tool that allows ASIC vendors to conduct on-site die size estimation and part quoting during initial meetings with potential customers. The company says the tool quickly generates PDF datasheets for side-by-side comparison of alternative combinations of IP blocks, macros and process technologies. SoC Plan encompasses hierarchical design planning and Verilog / VHDL entry for physical architectural-level planning, and for IP evaluation, selection and integration. The tool includes automatic and interactive floorplanning, IO placement and power planning capabilities, and continuous design analysis and refinement to meet physical constraints. SoC Prototype adds timing-driven block placement and automatic synthesis constraint generation capabilities to guide synthesis and gate-level handoff. An integral hierarchical timing budgeting algorithm extracts path information from the tool's virtual router to create realistic synthesis constraints that reflect delay through trial routes. LogicVision, Inc. announced that Agere Systems completed an 11-million gate SoC that contains LogicVision's embedded test structures. During the chip design phase of development, Agere says it used LogicVision's hierarchical architecture to integrate test controllers with the 200 clock domains in the functional logic. The company also says that at-speed verification of first samples was completed with the LogicVision Validator system in less than one day. Magma Design Automation Inc. announced that SynTest Technologies has joined the MagmaTies program to integrate its design-for-test (DFT) tools with Magma's RTL-to-GDSII IC design flow. SynTest and Magma will work together to establish a DFT flow that will include SynTest's DFT rule checking, boundary scan insertion, built-in self-test (BIST) technologies, and scan-based automatic test-pattern generation (ATPG) testing. The companies report this integration will complement Magma's existing scan-based DFT methodology and that they will work with mutual customers to validate the flow and bring it to production. Mentor Graphics Corp. announced Version 5 of the Seamless environment. The company says V5 extends the use of the tool beyond HW/SW co-verification to system performance analysis. New features are intended to help designers use the data available from co-verification to characterize and reduce system performance bottlenecks, and to meet performance specifications and verify hardware and software interfaces in a single environment. Also from Mentor Graphics - The company announced the release of two new Calibre products, Calibre FRACTUREj and Calibre FRACTUREt, which support the JEOLV52 and Toshiba VSB11 mask writing machines. The company says these tools expand Calibre's mask data preparation (MDP) tool portfolio for variable shaped beam (VSB) mask writing machines, a portfolio which includes Calibre FRACTUREm for the MEBES mask writing format, and Calibre MDPView. The company also says that this release is part of "Calibre's strategy to deliver a complete and unified design-to-silicon platform." Additional mask writer formats are being prepared for future release. Finally - Mentor Graphics Corp. also announced comprehensive design tool support for the Spartan-3 platform FPGAs from Xilinx, Inc. Additionally - Model Technology, which Dennis Brophy will tell you is a Mentor Graphics company, announced the availability of the ModelSim Version 5.7 tool. The company says this release offers "improved simulation performance, new debug capabilities, additional support for Verilog 2001, and new job-management functionality for simulation farms." Meanwhile - Accelerated Technology, the Embedded Systems Division of Mentor Graphics Corp., announced that components of the code|lab Embedded Developer Suite are now shipping in Altera Corp.'s Nios Development Kit, Stratix, and Cyclone Editions. The company says that inclusion of the development tools in the Nios kit provides developers with a comprehensive software debug environment for system-on-a-programmable-chip (SOPC) applications. Also from Accelerated Technology - The division announced that its Nucleus RTOS was used to develop a wireless point-of-sale (POS) terminal, the M.POS2002, for consumers in the Chinese financial transaction market. An initial order for 5,000 terminals will soon be delivered to a major corporation in Beijing. The M.POS2002 was developed by M.POS Ltd. in Hong Kong and is an electronic funds transfer POS capable of processing magnetic cards or smart card payments in real time from any location. The terminal can also capture and transmit data for corporate applications, and make voice calls and fingerprint verification. It also has text and e-mail messaging capabilities. MIPS Technologies announced that its 32-bit 4Kc core has been licensed by Infineon Technologies for development of "advanced communications systems" for the Internet Protocol phone market. Numerical Technologies, Inc. announced that it has signed a joint development agreement with Applied Materials, Inc. to study resolution enhancement technologies (RETs) for 193-nanometer lithography processes. The work, which is focused on providing semiconductor manufacturing tools for sub-100-nanometer chip production, will be done at Applied Materials' Maydan Process Module Technology Center in Sunnyvale, CA. Synplicity, Inc. announced support of Xilinx, Inc.'s new 90-nanometer Spartan-3 platform as well. The company says it has optimized its Synplify and Synplify Pro FPGA synthesis software, and that it continues to provide support for Xilinx's family of PLDs, while reaffirming its commitment to provide mutual customers with "RTL-based solutions tailored for Xilinx's high-density, low-cost programmable logic devices." TriCN announced that it has validated a range of TriCN products as "Ready for IBM Technology." This designation signifies that these TriCN interface products are compatible with IBM's 0.13-micron CMOS technology. TriCN says that products included in the classification range from base-level I/O cells to multi-gigabit interface products. Zenasis Technologies announced on April 7th that it has joined Synopsys' Milkyway Access Program (MAP-in). The companies say that, as a result, Zenasis timing closure technology and other tools will have a tighter interface with Synopsys tools and flows through a direct API into the Milkyway design database. Similarly, Teseda Corp. announced on April 7th that it has joined Synopsys' Milkyway Access Program. The companies say that through MAP-in, Teseda's Validator 500 and other DFT tools will have tighter integration with Synopsys' tools and flows through a direct API into the Milkyway database. And similarly, ReShape, Inc. announced on April 7th that it has joined Synopsys' Milkyway Access Program. The companies say that by joining MAP-in, ReShape gains access to the Milkyway database, Scheme interpreter, and API to move to multi-vendor interoperability with the GDS Builder system and other ReShape tools. Industry News - Devices Agere Systems announced April 7th that it is "the world's first company to deliver a production-qualified, communications chip using low-k dielectric 0.13-micron technology. This ultra-high performance, all-copper semiconductor technology significantly accelerates chip speed, reduces power consumption, and lowers electronics costs." The new chip has passed product and packaging qualifications at TSMC. Altera Corp. announced that its Stratix EP1S60 and Cyclone EP1C12 devices are now shipping. The company says, "The Stratix device family allows customers to address the challenges of building high-bandwidth systems, while the low-cost Cyclone device family delivers the flexibility customers need for their designs at ASIC-like prices." The move to volume production for both the Stratix and the Cyclone device families has hinged on the partnership between Altera and TSMC. The Stratix family is built on TSMC's all-copper, 0.13-micron process technology. The Cyclone family is based on the same process and represents three out of five devices now shipping in production. Taiwan Semiconductor Manufacturing Company (TSMC) announced new production data on its 0.13-micron processes as well as status for its 90-nanometer processes. The company reports more than 230 product designs taped out to its 0.13-micron processes and more than 100,000 0.13-micron wafers shipped to date. TSMC says it has recorded more than twenty customer projects at 90 nanometers that are at various design stages. Production for customers using TSMC's Nexsys 90-nanometer technology with copper and low-k dielectrics on 300mm wafers is expected to start in Q3 of 2003. Texas Instruments Inc. introduced a new family of low-noise (75nV), 24-bit data acquisition SoCs from the company's Burr-Brown product line which incorporates a quad 16-bit DAC and I2C interface. The MSC1211 family integrates a 24-bit delta-sigma ADC with an enhanced 8051 processor core, flash memory, and a variety of on-chip peripherals to achieve what the company calls "unparalleled system performance -- all at 4mW power consumption. The integration of the analog and digital cores gives customers the ability to customize the device to meet their specific requirements." Toshiba America Electronic Components, Inc. announced new multi-chip package (MCP) products which have five and six chips stacked inside ball grid array (BGA) packages to create single 9mm x 12mm x 1.6mm components. Toshiba will develop five- and six-chip MCPs with various combinations of NOR flash, NAND flash, static RAM (SRAM), and pseudo SRAM (PSRAM) to meet memory requirements in digital camera phones and 3G cell phones. Xilinx, Inc. announced a new family of programmable chips that the company says can be expected to "propel programmable logic devices further into high-volume, low-cost applications traditionally served by custom chips with fixed architectures." Xilinx says it is targeting a $23 billion market with its 90-nanometer Spartan-3 programmable chips. The new Spartan-3 family uses both 90-nanometer and 300-milimeter manufacturing technologies to yield what the company calls "unprecedented density and price for FPGAs." Xilinx also says that by setting "a new FPGA price-density standard the company will be able to address new, higher volume applications in the ASIC market." Coming soon to a theater near you Embedded Systems Conference - It's happening this week at Moscone Center in San Francisco, CA. The Technical Conference runs from April 22nd to the 26th and the Show Floor runs from April 23rd to the 25th. Here's what the organizers are saying: "Gain the fresh ideas, new perspectives, and skills you need to succeed. Invest in your career by attending the 15th Annual 2003 Embedded Systems Conference San Francisco. ESC San Francisco features 90 industry experts presenting 146 classes and tutorials all designed to help you gain fresh perspectives and the latest embedded skills. ESC San Francisco provides you with the tools you need to succeed now and in the long term. The technical conference focuses on helping you gain the practical knowledge and skills necessary to make your embedded designs better, faster, and more reliable. The show floor brings together leading companies exhibiting the hottest products in the embedded industry, allowing you to choose the best and most innovative solutions for your products." So, don't forget to go. Lots of people will be there. And lots of them, apparently, will be succeeding. Don't miss this chance to be one of them. ( www.esconline.com ) X-FAB Seminar - The semiconductor foundry is offering a free lunch and daylong technical seminar discussing "Intelligent Power Management Integration using High Voltage Processes and Dedicated Libraries." The event takes place on May 14th in Santa Clara, CA, and on May 15th in Irvine, CA. Presentation I will cover low power and low noise optimization of digital libraries for mixed-signal designs, the application and implementation of noise reduction circuit, and layout techniques to minimize digital noise level. Presentation II will cover high voltage options in MOS technologies, increasing the breakdown voltage of MOS transistors, how to make use of wide voltage ranges, and process technologies to effectively address high voltage options. ( www.xfab.com/english/news/seminar.html ) Newsmakers Agere Systems and Cadence Design Systems, Inc. announced they have donated the ChartReuse-II IP assessment program to VSIA. The companies say that ChartReuse-II provides continued enhancements to the OpenMORE IP assessment program previously donated to the Alliance. Both Agere and Cadence have joined the VSIA Quality Development Working Group (DWG) to work with the DWG's chairman and members, who have been working diligently toward the release of an updated Quality Assessment metric later this year. The VSIA Quality Metric will be released in Q3 2003 and will allow designers who adopt this standard to grade IP blocks containing soft and hard IP objectively. This will then be extended to embedded systems IP containing digital, verification, and software IP provided separately or as a system. Emulation and Verification Engineering announced Rob Eckelmann has joined its Board of Directors as Executive Director. Previously, Eckelmann was Vice President of Intel's Sales and Marketing Group and General Manager for Europe, Middle East, and Africa Operations. Earlier, Eckelmann served in the U.S. government, managing international trade policy and development in the technology sector. He has also served on various boards, including the Arizona State University School of Business, the Foreign Policy Association, and the German-American School of Portland, OR. Eckelmann has degrees from Princeton, the University of Chicago, and Williams College. Monarch Technologies Group announced a move to become a sales and marketing specialist for new and emerging EDA companies. The company says that it will offer a channel for exposing large numbers of consumers to new EDA products, and that it offers an "experienced, professional business team available to emerging companies looking to leverage growth by outsourcing their sales force." Company Founder Bill Hoolhorst said, "Contrary to the concept of farming out low-cost, commodity products to multiple manufacturer's reps and alternate channels, Monarch Technologies Group is, essentially, a high-end sales force for hire. We offer a ready-made, high-end sales force to new and emerging EDA companies that lack the funding to finance such an expensive undertaking." Summit Design, Inc. announced that Summit Design Japan Co. Ltd. has been formed to serve as Summit's first direct Japanese sales office. Summit Design has spent the last 10 years distributing its products in Japan through Seiko Instruments Inc., but as of April 1st the new office will serve as a direct channel to the Japanese marketplace. In the category of ... DAC 2003 Anaheim - Cultural Primer Part I Following are some well-intentioned bits of advice from a seasoned Northern Californian that may help ease your transition into the life and culture of Southern California. We start with some instructions in the local dialect. Freeway Speak - If you're from somewhere other than Southern California, you might say: "First you go South on 101, then East on 237." Or you might say: "First you go North on 680, then West on 24." But if you're at DAC and you're the one getting the instructions, you'll hear things like: "First you go North on THE 405, then East on THE 110, and then South on THE 5." Now this THE thing may seem like a small point to you, but you'll notice it right away - as soon as you land at LAX or at John Wayne. It's THE (freeway moniker) everywhere you go and you better get used to it. In fact, if you stay at DAC long enough, you'll start to doing the THE thing yourself, and you'll end up having to seek corrective help to break the habit after you return to your own metropolis. The Weather - This is another important subtlety in understanding the local culture across the entire L.A. basin. DAC Chair Ian Getreu points out that no matter what the weather conditions are on any particular day, and no matter what the season, Southern California natives will tell you, "This is really quite unusual." 45 minutes to anywhere - Ian also points out an equally important fact for anyone intending to motor about on THE anything. No matter where you're trying to get to, it's going to take 45 minutes. Driving from Disneyland to Long Beach? 45 minutes. Driving from Anaheim to Pasadena? 45 minutes. Driving to the corner drugstore to pick up some Alka Seltzer? 45 minutes. That's not to say, of course, that other metropolitan areas don't 'enjoy' a bit of traffic now and again. But across the L.A. basin - and this applies to Orange County as well - no matter where you're trying to get to, plan to take 45 minutes to get there. Unless, of course, it's rush hour. Then plan on 2 hours. Thunder Stix and the Rally Monkey - Far and away the single most important piece of advice in dealing with the natives of Southern California - eclipsing, in fact, all of the preceding pointers combined - is the following: First - Ask the person if they're from L.A. or from Orange County. Second - If they're from L.A., use a derisive laugh in referring to things like rally monkeys and thunder stix. Third - If they're from Orange County, use the name "David Eckstein" liberally in sentences that include phrases like David and Goliath, Bonds, Bottom of the 7th, and The greatest choke in the history of baseball. Fourth - If you discover they're neither from L.A. nor from Orange County, you can relax, diss the Dodgers, speak openly about future Hall of Famer Barry Bonds, and note out loud that it's not real baseball when it's played in a stadium where there's a waterfall out in Left Field. --Peggy Aycinena is a Contributing Editor and can be reached at peggy@ibsystems.com . You are subscribed as: [dolinsky@gsu.by]. EDAWeekly is a service for EDA professionals. EDAToolsCafe respects your online time and Internet privacy. If you would prefer not to receive this type of email or if you consider this message as unsolicited commercial e-mail, please click here . PLEASE NOTE: You can change the frequency of this newsletter by clicking here . If you have questions about EDAToolsCafe services, please send email to edaadmin@ibsystems.com . Copyright c 2002. Internet Business Systems, Inc. All rights reserved.